1. Field of the Invention
The present invention relates to an image data signal processor, and more particularly to an A/D conversion of an image data signal with a wide dynamic range in an image data signal processor.
2. Description of the Related Art
An image data signal processor is used to effectively widen the dynamic range (D) of an image data signal processing circuit, as shown in, for example, Japanese Laid Open Patent Disclosure (JP-A-Showa 62-116063: first conventional example).
FIG. 1 is a block diagram illustrating the structure of an the first conventional example of image data signal processor. Referring to FIG. 1, a sensor 107 is the sensor which inputs an image data signal. A clamp circuit 100 clamps the image data signal outputted from the sensor circuit 107 to the DC level which is given from an error amplifying circuit 106. A gain amplifier 101 amplifies the output of the clamp circuit 100 with a predetermined gain and a buffer circuit 102 buffers the analog image data signal outputted from the gain amplifier 101. An A/D converter 103 converts the image data signal outputted from the buffer circuit 102 into a digital data signal to output to a display unit. The display unit 108 displays digital image data.
A black level detecting circuit 104 detects a DC level for a black color of the analog image data signal outputted from the buffer circuit 102. A reference voltage generating circuit 105 generates a reference DC level. The error amplifying circuit 106 amplifies the difference between the output of the black level detecting circuit 104 and the reference voltage to output the amplifying result to the clamp circuit 100.
Next, the operation of this first conventional example of an image data signal processor will be described below.
An analog image data signal that is output from the sensor 107 is clamped by the clamp circuit 100 to fix a DC level. Then, the clamped image data signal is amplified with a predetermined gain by the gain amplifier 101. The amplified image data signal is supplied to the A/D converter 103 through the buffer circuit 102. The display unit 108 displays the digital image data outputted from the A/D converter 103.
When an image data signal is A/D-converted, it is desirable to use the dynamic range of the A/D converter 103 in the maximum. For this purpose, the output signal of the buffer circuit 102 is supplied to the black level detecting circuit 104. The black level detecting circuit 104 detects the black signal level of the image data signal outputted from the buffer circuit 102 to the error amplifying circuit 106. The error amplifying circuit 106 compares the predetermined DC level supplied from the reference voltage generating circuit 105 and the DC level of the black image data signal supplied from the black level detecting circuit 104. Then, the error amplifying circuit 106 amplifies the difference between them to output the amplified difference (error) as a clamp voltage to the clamp circuit 100.
In this case, the reference voltage of the reference voltage generating circuit 105 is previously set such that the black level outputted from the black level detecting circuit 104 is coincident with the minimum reference level of the A/D converter 103. Thus, the dynamic range of the A/D converter 103 can be effectively used and the black level of the image data signal can be revised.
However, there are the following problems in the above-mentioned first conventional example of an image data signal processor.
That is, first, there is a case where the dynamic range of the A/D converter 103 is not effectively used. In the conventional image data signal processor, the black level of the image data signal is adjusted to the lower reference voltage of the A/D converter 103 such that the amplitude of the image data signal is effectively allocated to the dynamic range of the A/D converter 103. However, since the maximum level of the image data signal is not detected, there is the case where the signal level of the image data signal is larger or smaller than the upper reference voltage of the A/D converter 103. In these cases, it cannot be accomplished that the image data signal is effectively allocated to the dynamic range of the A/D converter 103.
Second, there is a case where the image data signal is saturated. In the first conventional example of image data signal processor, the black level of the image data signal is adjusted to the lower reference voltage of the A/D converter 103 to effectively allocate the image data signal to the dynamic range of the A/D converter 103. However, since the maximum level of the image data signal is not detected, the image data signal is saturated, when the upper reference voltage of the A/D converter 103 is lower than the maximum level of the image data signal. As a result, the image data signal is impossible to be faithfully reproduced.
Also, a color video printer signal processing circuit is described in Japanese Laid Open Patent Application (JP-A-Heisei 2-200442), in which a DC level is fed back to a clamp circuit provided before an A/D converter such that the dynamic range of the A/D converter can be used in maximum.
In Japanese Laid Open Patent Application (JP-A-Heisei 2-254659), an image data signal processing circuit is described in which only a maximum value of the envelope after a reproduced RF signal is A/D-converted is detected and the maximum value is supplied to the A/D converter. Also, the detecting operation of the maximum value is performed for a predetermined time period, for example, when the mode of a system is changed from the stop mode to the reproduction mode.
In Japanese Laid Open Patent Application (JP-A-Heisei 3-106269), an image data signal processing apparatus is described, in which a ratio of pixels having a level higher than a predetermined level of a dynamic range to all pixels is calculated and the characteristics of an image data signal outputted from an image sensor are changed based on the calculated ratio.
In Japanese Laid Open Patent Application (JP-A-Heisei 3-131177), an image data signal processing circuit is described in which an image data signal is supplied to a multiplier via an amplifier and an A/D converter and an area value of an image data signal higher than a predetermined level which is near to a saturation level is detected. The gain of the amplifier is controlled based on the area value, and a peak value and average value of the output of the A/D converter.
In Japanese Laid Open Patent Application (JP-A-Heisei 6-319060), an image data signal processing circuit is described which is composed of an A/D converter, a filter circuit for a pilot burst signal, and a switch for selectively outputting one of the output of the A/D converter and the output of the filter circuit. In this conventional example, a sync chip level detecting circuit holds a DC component of an image data signal to output to the A/D converter and a predetermined voltage is also supplied to the A/D converter.